
IS  260 Data Base TheorySFCC Computing, Math Science Div.Paul Lecoq  InstructorOfice 18129A 5333793 1030 to 1130 MF Plus at least 12 hours of study & homework outside of class per weekThis course introduces Digital circuit design with an introduction to design software.LEARNING OBJECTIVES:You are expected to be able to do this before completing this CourseYou will understand the principles of Relational Data Base design and be able
to create an effective data base complete with forms and reports. You will
be able to apply principles of build or simulate, and test static, synchronous and asynchronous
digital systems suitable to complete imbedded microprocessor products.
You will gain experience in documenting what you do in the lab. BACKGROUND & DISCUSSIONDigital logic design has progressed from the relays of 1939 to SVLSI with thousands of transistors on a chip. Recent years have seen increased use of imbedded microprocessors and custom computerdeveloped PLDs. Imbedded microproccor system prevail in most designs today but time critical designs must be implemented in hard wired logic for maximum speed. In any case, the basics of digital logic design are the foundation for all digital systems.INSTRUCTIONS:What you are expected to do in this class?The course will include a significant amount of reading and design of many different kinds of digital systems. From the lectures you will find out what is most important and therefore, where to spend most of your time. You should read dilligently and experiment with hardware and simulator. Qusetions arrising from readings will be inswered in class. In the lab you will take on specific design problems, documenting each step of the development process. EVALUATION CRITERIA:How well have you done?Since this is a handson experience class the primary means of evaluating your understanding will be for me to watch you manipulate circuits in the laboratory. Your Lab Reports will confirm your understanding of what you have done. Exams will test your ability to solve problems by yourself. Lab assignments will give you experience and test your ability to work together with others.
Learning Objectives  You are expected to be able to do this before completing this CourseYou will design, build or simulate, and test static, synchronous and asynchronous digital systems suitable to complete imbedded microprocessor products. You will gain experience in documenting what you do in the lab. You will learn the rules of connectivity for 7400 logic family gates and be aware of variations in the 7400 family. You wil also learn to design, build, and troubleshoot selected computer components and standalone digital systems using standard design and simplification techniques such as Boolean algebra, Carnaugh maps, and various timing diagrams. Back
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What you are expected to do in the lecture part of the class?The course will include a significant amount of reading and design of many different kinds of digital systems. From the lectures you will find out what is most important and therefore, where to spend most of your time. You should read dilligently and experiment with hardware and simulator. Your success in this class has to do with how much time you spend reading, doing exercises, and interacting with the instructor and classmates. . I, as the instructor, can't check every step of your progress. You will have to try the assignments in the book and those I give you. When you run across problems understanding the book or lectures, bring the problems to class for discussion. A Midterm and a Final exam will sample your knowledge but watching you perform will provide a better measure of your success.Read the book, do the exercises, and let me know how well you are doing.
What you are expected to do in the lab?. In the lab you will take on specific design problems, documenting each step of the development process.Each laboratory exercise will lay out a specific problem to solve. You will use standard techniques to find a solution to the problem, propose aleternate designs from which you will choose the most effective. You will then design the circuit completely, simplifying it if appropriate, and completely document the design. The next step is to build and test the circuit, recording problems found in building and testing. Laboratory Report format:Most lab will require considerable prior preparation. Please show the instructor your lab prep documentation at the beginning of the lab. Preparatory items are indicated below with *.For each assignment listed below you will each create a lab report similar to the following.
Weekly schedule of events.Complete reading before week noted!Assignments are due on the first class day of the week noted. (eg. Assignment 1 is due on 8 Jan)
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How do you know when you are done? How well have you done?Since this is a handson experience class the primary means of evaluating your understanding will be for me to watch you manipulate circuits in lab. The assignments are meant to focus your learning on specific important subjects but just because I haven't assigned a subject explictly doesn't mean that you shouldn't know it. If it is in the reading assignment or lectures, it is important.The Exams will sample the depth of your understanding in representative areas. But don't forget that much of what we work on this quarter will soon be obsolete so the most important thing for you to do will be to learn how to learn. Worst Case Grading criteria
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Lab Assignment 1
This initial lab is to familiarize you with
the basic operation of logic gates. You will always do a complete
logic diagram with pin numbers specified before you begin to 1. Obtain the following gates and install them on a breadboard.
Validate the operation of the gates: AND, OR, Inverter, NAND, NOR, Exclusive OR 2. Following are some Boolean equations and some truth tables.
Some equations are POS, some are SOP, some are Canonical, some are none of the
above. Build the circuits for the left hand truth tables and the equations for X, Y, and P. Validate the truth tables for each circuit you build.
Multilevel gate circuits  Use of one gate type Objectives: Minimize and implement the following in both ANDORNOT logic. Implement X and Z as NAND only circuits and Y and Q as all NOR circuits X = (A+B)(AB+C)' Y = A(B'C + B) + B(A'B +C) Z = A'(B(C'+D)+(A'D+C) + (BC) Q = (AB+AC' )(B+C) (Do not minimize this) Build a circuit that will produce four outputs (A,B,C,D) from two inputs where: A will be false for only the 0_{d}
input Return to the schedule
Assignment 3Mux/demux, Arithmetic
MUX logic Minimize the following equations using both Boolean algebra and K Maps.
X = (A'+B'+C'+D') (A+B'+C'+D') (A'B'CD') Y = A'B'C'D' + A'B'CD' + A'BCD + ABC'D + AB'CD' ADDER design a two bit adder/subtractor with input carry both in random logic and with the use of half adders. (Use of XOR is permissible) Implement and test the random logic version. BCD Divider A four bit BCD digit (09) when divided by five will yield a one bit quotient (Q) and a three bit remainder (R_{2}, R_{1,}R_{0}). Design a circuit which will execute the division. Show the unminimized circuit then use a KMap (include it in the prelab documentation) to minimize it. Implement and validate the operation of the circuit. Return to the schedule
Assignment 4 Latches and Flip FlopsCIn this laboratory you will explore the simple memory devices, latches and D flipflops.1. Latches: These devices provide single bit memory functions as well as acting as a debounce circuit for undampt mechanical switches. You are to do what you have to do to understand this circuit thoroughly.
2. Gated D FlipFlop: Add the necessary steering circuitry to the nand latch above to convert it to a gated D flipflop. This is a level gated D flipflop.
What is the difference between a level triggered FlipFlop and an edge triggered FlipFlop? Why would one choose one over the other in any application? Using either an open collector or tristate bus driver, connect four of these flipflops up as one bit registers connected to one bus line.. Preset the flipflops to 1 0 0 1 for registers A, B, C, and D. Using the appropriate trigger and output gate to transfer the data in A to the C register. Transfer data from the D register to the C Register Transfer the B register data to the D register. Illustrate how this is equivalent to moving data around inside a computer. Demonstrate how this circuit to be RAM memory cells in the computer. Return to the schedule Return to topConstruct a divide by 8 ripple up counter and test it thoroughly. Modify the ripple counter to count down Add flip flops to the counter to produce a divide by 16 up counter Modify the divide by 16 to make it a BCD counter
Return to topLab Assignment 5. Synchronous Counters and shift registers
Lab Assignment 6. Lab Assignment 6.  Return to topLab Assignment 7. AddersIn this exercise you will explore several aspects of arithmetic adders.
You will examine the basic Boolean requirements, then examine three ways of
implementing it.
* Build and test Return to topLab Assignment 8. Finite State AutomataThe Ethernet protocol can be implemented with a simple Finite State Automoton. In the Idle state the node transmitter is prepared to accept a message to be sent. Its ready output is true. Upon receiving a Message command from the computer it switches to the Message to send State. When the message buffer is full and the message can be sent, the system switches to the Network Busy? state at which time the system's ready signal goes false. The network is tested in this state. If it is busy, the system goes to Wait Rand time state and waits for a random amount of time before it switches to Message to send state. It then goes immediately to Network Busy? state where it tests the network. If it is busy the system waits again. If not busy it transmits the message over the network from the Transmit State. If at any time during Transmit state, the system detects a collision, (Another node tried transmitting at the same time) the system goes back to the Wait Rand time state to try again a while later. The random time assures that the colliding nodes won't try to transmit at the same time again. If the transmit is completed without collision, set ready to true and switch to Idle state. Construct a State diagram of this FSA. Using flipflops and gates, design and implement a machine that implements the state diagram and the bubble diagram. Inputs: Message Command, buffer full busy, collision, transmission complete. Outputs: ready, transmit enable
Return to topLab Assignment 9. Return to topLabAssignment 10. Return to topLab Assignment 11. Return to topLab Assignment 12. Final ProjectReturn to topLecture Assignment 1. Combinatorial Logic Lecture assignment 1, due at the beginning of week 3
Lecture Assignment 2. Lecture assignment: Chapter 4  4.1, 4.8 A Explain the operation of a 4 bit 2’s complement adder/ subractor. Illustrate with truth tables and figures if appropriate. What are the consequences of the four permutations of the overflow bit? B. A box has two data inputs, A
and B and two outputs A and B. Chapter 5  5.8, 5.19, 5.24 Latches, flipflops, counters Latches: Discuss the operation of latches thoroughly. How may they be used in real world situations?FlipFlops: Discuss and document the operation of the standard D FlipFlop (7474) Ripple Counters:
Return to topLecture Assignment 3. Dish Washer ControllerIn this discussion we will design a complete controller for a simulated dishwasher with 9 controllable cycles and two wash settings. We will first define the timing then design a circuit which will execute all appropriate functions. Timing:
Return to topLecture Assignment 4. Finite State AutomataFSAs are very useful when the circuit is inherently sequential. One feature is that they are readily implemented in a PLA or Programmable Logic array. Read the first part of chapter 8 and practice doing the bubble charts and state tables. In class we will develop a system which will count 1 6 4 (975)*3 2 0... Return to topLecture Assignment 1. Return to topLecture Assignment 1. Return to topUseful computer toolsCarnaugh Map of four variables
