IS - 260  Data Base Theory

SFCC Computing, Math Science Div.

Paul Lecoq - Instructor

Ofice 18-129A 533-3793

1030 to 1130 M-F

Plus at least 12 hours of study & homework outside of class per week

This course introduces Digital circuit design with an introduction to design software.

LEARNING OBJECTIVES:

You are expected to be able to do this before completing this Course

You will understand the principles of Relational Data Base design and be able to create an effective data base complete with forms and reports.  You will be able to apply principles of build or simulate, and test static, synchronous and asynchronous digital systems suitable to complete imbedded microprocessor products. You will gain experience in documenting what you do in the lab.
You wil also learn to design, build, and troubleshoot selected computer components and stand-alone digital systems using standard design and simplification techniques such as Boolean algebra, Carnaugh maps, and various timing diagrams.

BACKGROUND & DISCUSSION

Digital logic design has progressed from the relays of 1939 to SVLSI with thousands of transistors on a chip. Recent years have seen increased use of imbedded microprocessors and custom computer-developed PLDs. Imbedded microproccor system prevail in most designs today but time critical designs must be implemented in hard wired logic for maximum speed. In any case, the basics of digital logic design are the foundation for all digital systems.

INSTRUCTIONS:

What you are expected to do in this class?

The course will include a significant amount of reading and design of many different kinds of digital systems. From the lectures you will find out what is most important and therefore, where to spend most of your time. You should read dilligently and experiment with hardware and simulator. Qusetions arrising from readings will be inswered in class. In the lab you will take on specific design problems, documenting each step of the development process.

EVALUATION CRITERIA:

How well have you done?

Since this is a hands-on experience class the primary means of evaluating your understanding will be for me to watch you manipulate circuits in the laboratory. Your Lab Reports will confirm your understanding of what you have done. Exams will test your ability to solve problems by yourself. Lab assignments will give you experience and test your ability to work together with others.





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Learning Objectives ---- You are expected to be able to do this before completing this Course

You will design, build or simulate, and test static, synchronous and asynchronous digital systems suitable to complete imbedded microprocessor products. You will gain experience in documenting what you do in the lab.

You will learn the rules of connectivity for 7400 logic family gates and be aware of variations in the 7400 family.

You wil also learn to design, build, and troubleshoot selected computer components and stand-alone digital systems using standard design and simplification techniques such as Boolean algebra, Carnaugh maps, and various timing diagrams.

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To be completed


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What you are expected to do in the lecture part of the class?

The course will include a significant amount of reading and design of many different kinds of digital systems. From the lectures you will find out what is most important and therefore, where to spend most of your time. You should read dilligently and experiment with hardware and simulator.

Your success in this class has to do with how much time you spend reading, doing exercises, and interacting with the instructor and classmates. . I, as the instructor, can't check every step of your progress. You will have to try the assignments in the book and those I give you. When you run across problems understanding the book or lectures, bring the problems to class for discussion. A Midterm and a Final exam will sample your knowledge but watching you perform will provide a better measure of your success.

Read the book, do the exercises, and let me know how well you are doing.

  • You are to follow the reading assignments in the table below without being reminded as the course goes on. Don't expect me to remind you.
  • You will convince yourself that you can answer the questions and do the basic exercises at the end of each assigned chapter.
  • You will do additional assignments as indicated in the table below.
  • You will have one Midterm exam and one final exam.
  • If you have had extensive experience and find the assignments unchallenging you may submit a contract to me to do other, more challenging, projects in their place as long as the substitute projects cover all the required material. See me about this.

What you are expected to do in the lab?

. In the lab you will take on specific design problems, documenting each step of the development process.

Each laboratory exercise will lay out a specific problem to solve. You will use standard techniques to find a solution to the problem, propose aleternate designs from which you will choose the most effective. You will then design the circuit completely, simplifying it if appropriate, and completely document the design. The next step is to build and test the circuit, recording problems found in building and testing.

Laboratory Report format:

Most lab will require considerable prior preparation.  Please show the instructor your lab prep documentation at the beginning of the lab.  Preparatory items are indicated below with *.For each assignment listed below you will each create a lab report similar to the following.
Date Name *
Lab Assignment number, Title *
Brief statement of the problem to be solved *


Initial specifications *


Design approach *

Design alternative A *
Design alternative B (as appropriate)
Design alternative C (as appropriate)
Boolean algebra- *
Including simplifications as appropriate

Boolean algebra-
Including simplifications as appropriate
Boolean algebra-
Including simplifications as appropriate
Circuit diagram *

Circuit diagram
Circuit diagram
Which alternative did you choose? Why did you choose it? *

Simplification process -  * Include truth tables, boolean simplification, Carnaugh Maps, etc.

Final Boolean algebra *

Final logic diagram including all pin numbers, IC types, chip numbers. 
Power and ground connections not required
Final wiring diagram *
Power and ground connections ARE required
Parts list *

Test plan *

Test results
( tables in which to record data *)
(Describe the operation and any discoveries you made)
(Describe any changes you made to the circuit or approach)
(Troubleshooting notes)
How would this circuit be used in industry?

Summary/Conclusions











Weekly schedule of events.

Complete reading before week noted!

Assignments are due on the first class day of the week noted.  (eg. Assignment 1 is due on 8 Jan)

Week

Subject----------------
Reading Lecture
Assignments
Lab
Assignments

1    W

3 Jan

     

2  MW

8 Jan
       

3  W

17 Jan
 
       

4  MW

22 Jan
       

5  MW

29 Jan
       

6  MW

5 Feb
       

7  MW

12 Feb
       

8  W

21 Feb
       

9  MW

26 Feb
       
10  MW
5 March
       
11  MW
12 March
       
10  MW
19 March
Final Examinations Week
--
 





* Each asterisk stands for one day missed that week for holidays or other reason.

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How do you know when you are done? How well have you done?

Since this is a hands-on experience class the primary means of evaluating your understanding will be for me to watch you manipulate circuits in lab. The assignments are meant to focus your learning on specific important subjects but just because I haven't assigned a subject explictly doesn't mean that you shouldn't know it. If it is in the reading assignment or lectures, it is important.

The Exams will sample the depth of your understanding in representative areas. But don't forget that much of what we work on this quarter will soon be obsolete so the most important thing for you to do will be to learn how to learn.

Worst Case Grading criteria

Two exams 300
About six formal assignments 300
Total 600
Exams - ~80% for 4.0 50% for 0.0

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Lab Assignment 1
Validating gate operation, simple circuits
Sum of products, Product of sums

This initial lab is to familiarize you with the basic operation of logic gates. 
You are to validate the operation of  the basic gates then use them in several multi-gate circuits.
You will manipulate SOP and POS equations and implement the results.

You will always do a complete logic diagram with pin numbers specified before you begin to
wire anything.

1.   Obtain the following gates and install them on a breadboard.  Validate the operation of the gates:
from the book, find the lowest 74xx number for each of these gates, draw the diagram, and fill in the
truth table from what you measure at the circuit.

AND, OR, Inverter, NAND, NOR, Exclusive OR

2.  Following are some Boolean equations and some truth tables.  Some equations are POS, some are SOP, some are Canonical, some are none of the above.
Render each of them in POS and SOP form.  Draw the logic block diagrams for each and the anticipated truth tables for each equation. 
Wire the following circuits up and verify that the observed results agree with the calculated results from the equations.

Build the circuits for the left hand truth tables and the equations for X, Y, and P.  Validate the truth tables for each circuit you build.





Lab assignment 2.

Multi-level gate circuits  --  Use of one gate type

Objectives:
Design, simplify, and implement multi-level circuits
Implement equivalent circuits in AND-OR-NOT and all NAND environments

Minimize and implement the following in both AND-OR-NOT  logic.
Document all steps

Implement X and Z as NAND only circuits and Y and Q as all NOR circuits

X = (A+B)(AB+C)'

Y = A(B'C + B) + B(A'B +C)

Z = A'(B(C'+D)+(A'D+C) + (BC)

Q = (AB+AC' )(B+C)      (Do not minimize this)

Build a circuit that will produce four outputs (A,B,C,D) from two inputs where:

      A will be false for only the 0d input
      B will be false for only the 1d input
      C will be false for only the 2d input
      D will be false for only the 3 input

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Assignment 3----Mux/demux, Arithmetic-----

 

MUX logic

Minimize the following equations using both Boolean algebra and K Maps. 
Design the circuits using both standard logic and 3 input MUX.
Implement and test the X circuit.

X = (A'+B'+C'+D') (A+B'+C'+D') (A'B'CD')

Y = A'B'C'D' + A'B'CD' + A'BCD + ABC'D + AB'CD'

ADDER

design a two bit adder/subtractor with input carry both in random logic and with the use of half adders. (Use of XOR is permissible)

Implement and test the random logic version.

BCD Divider

A four bit BCD digit (0-9) when divided by five will yield a one bit quotient (Q) and a three bit remainder (R2, R1,R0).  Design a circuit which will execute the division.  Show the unminimized circuit then use a KMap (include it in the prelab documentation) to minimize it.  Implement and validate the operation of the circuit.

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Assignment 4  ----Latches and Flip Flops-----C

In this laboratory you will explore the simple memory devices, latches and D flip-flops.

1.  Latches:  
These devices provide single bit memory functions as well as acting as a debounce circuit for undampt mechanical switches.  You are to do what you have to do to understand this circuit thoroughly.
  • Start by designing, building, and testing both a nand latch and a nor latch.  Test it thoroughly and write a short description of the operation of each for your lab report. Show in your report how a latch might be used as a memory device.
  • Show in your report how a latch might be used as a debounce circuit.  How does it perform this useful function?
  • What is the inherent limitation of the latch when used for memory?

2.  Gated D Flip-Flop:   Add the necessary steering circuitry to the nand latch above to convert it to a gated D flip-flop.  This is a level gated D flip-flop.
  • Describe the operation of the flip-flop as a part of your lab report
  • Build and test the flip-flop
  • Show how this flip-flop would be used to store data.
3.  Edge triggered D Flip-Flop:  Find a dual edge triggered D Flip-Flop in the catalog of 7400 circuits.   Study and describe its operation.
What is the difference between a level triggered Flip-Flop and an edge triggered Flip-Flop?   Why would one choose one over the other in any application?
Using either an open collector or tri-state bus driver, connect four of these flip-flops up as one bit registers connected to one bus line..  
Preset the flip-flops to 1 0 0 1  for registers A, B, C, and D.
Using the appropriate trigger and output gate to transfer the data in A to the C register.
Transfer data from the D register to the C Register
Transfer the B register data to the D register.
Illustrate how this is equivalent to moving data around inside a computer.
Demonstrate how this circuit to be RAM memory cells in the computer.


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Construct a divide by 8 ripple up counter and test it thoroughly.
    Demonstrate effects of bouncing switches by removing the debounce circuit

Modify the ripple counter to count down

Add flip flops to the counter to produce a divide by 16 up counter

Modify the divide by 16 to make it a BCD counter

 

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Lab Assignment 5.  Synchronous Counters and shift registers

  1. Create a divide by 4 synchronous Gray code counter with symmetric output.  Test it thoroughly
  2. Decode the counter such that you obtain a distinct separate output for each of the four times segments.
  3. Connect the counter to the function generator using the circuit above.  Verify correct counting of the counter.  Does the circuit still need a debouncer?
  4. Build a four step shift register into a parallel to serial converter. use JK flip-flops.   Hook it up to the signal generator and show how one can transmit four bits at a time in parallel.

 



Lab Assignment 6.


Lab Assignment 6. -------

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Lab Assignment 7. ---Adders----

In this exercise you will explore several aspects of arithmetic adders.  You will examine the basic Boolean requirements, then examine three ways of implementing it.
Perform the following:

  • Design a full three input adder using nand logic
  • Create a half adder and test it thoroughly *
  • Create a full adder from half adders and test it thoroughly *
  • Create a two bit ALU capable of adding and subtracting *

* Build and test

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Lab Assignment 8. ---Finite State Automata----

The Ethernet protocol can be implemented with a simple Finite State Automoton.  

In the Idle state the node transmitter is prepared to accept a message to be sent.  Its ready output is true.  Upon receiving a Message command from the computer it switches to the Message to send State.  When the message buffer is full and the message can be sent, the system switches to the Network Busy? state at which time the system's ready signal goes false.  The network is tested in this state.  If it is busy, the system goes to Wait  Rand time state and waits for a random amount of time before it switches to Message to send state.  It then goes immediately to Network Busy? state where it tests the network.  If it is busy the system waits again.  If not busy it transmits the message over the network from the Transmit State.  If at any time during Transmit state, the system detects a collision, (Another node tried transmitting at the same time) the system goes back to the Wait Rand time state to try again a while later.  The random time assures that the colliding nodes won't try to transmit at the same time again. If the transmit is completed without collision, set ready to true and switch to Idle state.

Construct a State diagram of this FSA.  Using flip-flops and gates, design and implement a machine that implements the state diagram and the bubble diagram.  

Inputs:    Message Command, buffer full busy, collision, transmission complete.

Outputs:  ready, transmit enable

 

 

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Lab Assignment 9. -------

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LabAssignment 10. -------

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Lab Assignment 11. -------

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Lab Assignment 12. -------Final Project

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Lecture Assignment 1. ---Combinatorial Logic -

Lecture assignment 1, due at the beginning of week 3

From the textbook pages 47-51:

Problems 2.3,  2.4,   2.8,   2.13,   2.18
 

From textbook pages 74-76

Problems 3.10,  3.11,  3.15,  3.17,  3.22
 

Write a brief justification for using only NAND gates in switching logic circuits.  How does it work?  Why does it work?  

 

 






Lecture Assignment 2. ---

Lecture assignment:

Chapter 4  --  4.1, 4.8   

 A      Explain  the operation of a 4 bit 2’s complement adder/ subractor.  Illustrate with truth tables and figures if appropriate.  What are the consequences of the four permutations of the overflow bit?

 B.     A box has two data inputs, A and B and two outputs A and B.
Design a circuit that will reliably allow the user to select channel A or B and move it from input to output.

Chapter 5   --- 5.8, 5.19,   5.24

 

 

Latches, flip-flops, counters ----

Latches:  Discuss the operation of latches thoroughly.  How may they be used in real world situations?

Flip-Flops: Discuss and document the operation of the standard D- Flip-Flop (7474)

Ripple Counters:
  • Show how D flip-flops may be used to construct a four bit register
  • Ripple counters
  • Show how you would design a four bit counter that counts 01230123...
  • Show how you would design a four bit counter that counts  32103210...
  • Show how you would design a four bit counter that counts 01234567890123456789...
  •     How can you make a counter that does not have the problem with rippling zeros?

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Lecture Assignment 3. --Dish Washer Controller-----

In this discussion we will design a complete controller for a simulated dishwasher with 9 controllable cycles and two wash settings.  We will first define the timing then design a circuit which will execute all appropriate functions.

Timing:
Cycle 0:    Everything is off
Cycle 1:    Preparation, empty the dishwasher

Cycle
Number
Name of cycle Actuator Time for this cycle
0 Washer is off.  No controls are running   None
1 Preparation A -  Reset everything. Reset  
2 Preparation B - drain water with low speed pump Low speed pump
Exhaust valve
 
3 Fill cycle.  Fill with fill valve Fill Valve  
4 Wash cycle - Recycle with high speed pump High speed pump
Recycle valve
 
5 Drain cycle - drain water Low speed pump
Exhaust valve
 
6 Fill cycle.  Fill with fill valve Fill Valve  
7 Rinse cycle High speed pump
Recycle valve
 
8      
9      

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Lecture Assignment 4. ---Finite State Automata----

FSAs are very useful when the circuit is inherently sequential.  One feature is that they are readily implemented in a PLA or Programmable Logic array.  Read the first part of chapter 8 and practice doing the bubble charts and state tables.  In class we will develop a system which will count 1 6 4 (975)*3 2 0... 

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Lecture Assignment 1. -------

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Lecture Assignment 1. -------

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Useful computer tools

Carnaugh Map of four variables


Two, Three and Four variable truth tables

Here is a gate template you might want to use

PAL example:


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