Engineering 190 Digital Logic

SFCC Computing, Math Science Div.

Winter 2016 Paul Lecoq - Instructor

Office 18-129A 533-3793

All communications for this class use email  
     paull@spokanefalls.edu        Start subject line with 190, or I may lose your email in the spam!

General email paull@spokanefalls.edu

Required Text Required Software

Course Text: --- Fundamentals of Digital logic

With Verilog Design

Third edition    -- Stephen Brown  & Zvonko Vranesic

Click here for
Zip file with required software

Click here for Cedar

Needed s

Rectabular Extursion

Your commitment to the class:

3:20-6:30 PM  Bldg 18, room 129
Within this time period will be an average of four hours of lecture/discussion and three hours of lab.  Labs will be scheduled within this period as appropriate.

Plus at least 12 hours of study and design outside of class per week

This course introduces Digital circuit design with an introduction to design software.

Item

LEARNING OBJECTIVES:

You are expected to be able to do this before completing this Course

You will design, build or simulate, and test static, synchronous and asynchronous digital systems suitable to complete imbedded microprocessor products. You will gain experience in documenting what you do in the lab.
You wil also learn to design, build, and troubleshoot selected computer components and stand-alone digital systems using standard design and simplification techniques such as Boolean algebra, Carnaugh maps, and various timing diagrams.

You will also learn to use Quartus and Verilog, industry standards,  to design and test complex circuits

Item

BACKGROUND & DISCUSSION

Digital logic design has progressed from the relays of 1939 to VLSI with thousands or millions of transistors on a chip. Recent years have seen increased use of imbedded microprocessors and custom computer-developed CPLDs. Imbedded microproccor system prevail in many designs today but time critical designs must be implemented in hard wired logic for maximum speed. In any case, the basics of digital logic design are the foundation for all digital systems.

Gate design capture, once the standard design tool for digital logic has largely been replaced by High Level Design Languages. As high level programming languages replaced Assembly language programming, programming languages are becoming the standard digital design methodology. However, you will be expected to understand gate-level digital design in order to understand the design languages.

Item

INSTRUCTIONS:

What you are expected to do in this class?

The course will include a significant amount of reading and design of many different kinds of digital systems. From the lectures you will find out what is most important and therefore, where to spend most of your time. You should read dilligently and experiment with hardware and simulator. Qusetions arrising from readings will be inswered in class. In the lab you will take on specific design problems, documenting each step of the development process.

You will be expected to be able to use Verilog, a HLDLs to implement complex circuits.

Item

EVALUATION CRITERIA:

How well have you done?

Since this is a hands-on experience class the primary means of evaluating your understanding will be for me to watch you manipulate circuits in the laboratory. Your Lab Reports will confirm your understanding of what you have done. Exams will test your ability to solve problems by yourself. Lab assignments will give you experience and test your ability to work together with others.





Back to Table of Modules










Objectives

Learning Objectives ---- You are expected to be able to do this before completing this Course

You will design, build or simulate, and test static, synchronous and asynchronous digital systems suitable to complete imbedded microprocessor products. You will gain experience in documenting what you do in the lab.

You will learn the rules of connectivity for 7400 logic family gates and be aware of variations in the 7400 family.

You wil also learn to design, build, and troubleshoot selected computer components and stand-alone digital systems using standard design and simplification techniques such as Boolean algebra, Carnaugh maps, and various timing diagrams.

You will be expected to design and test circuits using Quartus and Verilog.

Back




bd


To be completed


Back




What you are expected to do in the lecture part of the class?

The course will include a significant amount of reading and design of many different kinds of digital systems. From the lectures you will find out what is most important and therefore, where to spend most of your time. You should read dilligently and experiment with hardware and simulator.

Your success in this class has to do with how much time you spend reading, doing exercises, and interacting with the instructor and classmates. . I, as the instructor, can't check every step of your progress. You will have to try the assignments in the book and those I give you. When you run across problems understanding the book or lectures, bring the problems to class for discussion. A Midterm and a Final exam will sample your knowledge but watching you perform will provide a better measure of your success.

Read the book, do the exercises, and let me know how well you are doing.

  • You are to follow the reading assignments in the table below without being reminded as the course goes on. Don't expect me to remind you.
  • You will convince yourself that you can answer the questions and do the basic exercises at the end of each assigned chapter.
  • You will do additional assignments as indicated in the table below.
  • You will have one Midterm exam and one final exam.
  • If you have had extensive experience and find the assignments unchallenging you may submit a contract to me to do other, more challenging, projects in their place as long as the substitute projects cover all the required material. See me about this.
Homework: Normally due at start of class on Tuesdays
      Assignment is  the minimum requierement. It would be hlepful to assure yourself that you understand all the problems at end of chapter, and to work out all examples.
      Assignment format:     Name, Date, and assignment number.  Do the problems in numerical order as assigned.

What you are expected to do in the lab?

. In the lab you will take on specific design problems, documenting each step of the development process.

Each laboratory exercise will lay out a specific problem to solve. You will use standard techniques to find a solution to the problem, propose aleternate designs from which you will choose the most effective. You will then design the circuit completely, simplifying it if appropriate, and completely document the design. The next step is to build and test the circuit, recording problems found in building and testing.

Lab reports for each week's lab are due at beginning of  class on the following Tuesday.  Late labs are subject to a 20% late penalty.

Laboratory Report format:

Most labs will require considerable prior preparation.  Please show the instructor your lab prep documentation at the beginning of the lab.  Preparatory items are indicated below with *.For each assignment listed below you will each create a lab report similar to the following.
Date          Name *
Lab Assignment number, Title *
Brief statement of the problem to be solved *


Initial specifications *


Design approach *

Design alternative A *
Design alternative B (as appropriate)
Design alternative C (as appropriate)
Boolean algebra- *
Including simplifications as appropriate

Boolean algebra-
Including simplifications as appropriate
Boolean algebra-
Including simplifications as appropriate
Circuit diagram *

Circuit diagram
Circuit diagram
Which alternative did you choose? Why did you choose it? *

Minimization  process -  * Include truth tables, boolean simplification, Carnaugh Maps, etc.

Final Boolean algebra *

Final logic diagram including all pin numbers, IC types, chip numbers. 
Power and ground connections not required
Final wiring diagram *
Power and ground connections ARE required
Parts list *

Test plan *

Test results
( tables in which to record data *)
(Describe the operation and any discoveries you made)
(Describe any changes you made to the circuit or approach)
(Troubleshooting notes)
How would this circuit be used in industry?

Summary/Conclusions

I expect you to execute an explicit schematic, fully annotated diagram with pin numbers BEFORE you begin to wire any circuit.  This would be a good example of such a pre-build drawing.
Sample Logic Diagram
"Images\samplelogic.jpg"





Wickipedia provides some background and history for the devices. They even give you an idea of how TTL works.

Go to one of the following sites to find the data sheets for digital devices we will be using.
   Rabbit
   Gauss
   U. Hawaii

Here are a few specific devices you may find useful
7483 Full Adder
74139 Decoder/Demux
74153 Mux
74190 Up/down Counter

Weekly schedule of events.

Complete reading before week noted!

Assignments are due the beginning of the week shown.

Week

Subject----------------
Reading   Lab
Assignments

1    

5 Jan

7 Jan

How does digital logic fit into the design
of a modern computer?
Variables, functions, inversions, truth tables
logic gates   Binary numbers, ASCII

Boolean Algebra
Design concepts -- synthesis with And, Or, Not
Begin logic design from truth tables
Chap 1
Read all of chapter 1
by Thursday
  Lab 1    Lab Instructions
             Lab Trainer
             Basic gates

2  

12 Jan

14 Jan


Standard gates and simple circuits
More complex circuits
SOP, POS, Canonical form
Minterm & Maxterm representations
Boolean Minimization
Practical minimization and optimization
Synthesis NAND, NOR
Homework due
1.1, 1.4, 1.6 1.8
Convert to ASCII binary
"1. Hello World?"

Through 2.6


  Lab 2  Combinational Logic with basic gates

Lab 3  Logic Implementation with one gate type


3  

19 Jan 

21 Jan 

Karnaugh Maps


MUX, DEMUX, encoders, decoders
Homework due
Ch 2 probs 1, 2, 3 ,7, 8, 20, 23, 32,33,37,38
Chap 3


  Lab 4:  Logic simplification with K-Maps

4  

26 Jan

28 Jan


Problem assignment due the week before the Midterm

Chapter 2

34,  37, 38, 41, 45, 48, 50, 54, 55,

60, 63, 66, 71, 73

 

Chapter 3

1, 2, 3, 4, 5,

 

Chapter 4

1-7,  10, 11, 13, 14, 18-22, 29, 31

Multilevel circuits factoring
Combinational-circuits
Multiple Output systems  
Intro to CAD tools (Verilog)

Number systems
Arithmetic circuits
Arithmetic circuits using Verilog

Chapt 4
Through 4.5



  3-S
   (with an adder)
MUX/DEMUX

5  

2 Feb



4 Feb

BCD, ASCII, & other codes
Combinational Circuits
Transistor switches, gate families
PLDs

MIDTERM EXAM
(up through 5.3)

Latches
Flip-flops, registers, counters,

Chap 4
Through 4.7
'Read' to end of 4
Chapt 5
through 5.3
Read rest of chapt

  4 - Latches &
registers

6  

9 Feb

11 Feb


 Sequential logic in Verilog
Master/slave, edge triggered FF

  Synchronous Sequential Circuits
Intro to Finite State Automata

Chap 6
to end
  5 - Counters

7  

16 Feb

18 Feb

Finite State Automata

Asynchronous sequential circuits
Storage elements
Chap 7
through 7.11
  6 - FSAs
Issue class proj.

8  

23 Feb

25 Feb


Bus architectureAsynchronous & Synchronous counters
Digital System Design
Chap 7
through end
 

9  

1 Mar

3 Mar


How a computer works
Major digital systems

Chapt 8,9
all
 

 

10  
8 Mar

10 Mar
System Design      Quarter Project
11 

15 Mar

17 Mar
catch up and review

All labs due this Wednesday -- Completed
Begin demonstrating projects
-----------   Demonstrate
Quarter Project
10  
22 Mar

Final Examination


but I will be here both days to answer questions and view projects

Final exam on Tuesday, 22 Mar. regular class time    
Demonstrate all  projects by end of day Tuesday

.

--    Demonstrate Project





* Each asterisk stands for one day missed that week for holidays or other reason.

Back




ec

How do you know when you are done? How well have you done?

Since this is a hands-on experience class the primary means of evaluating your understanding will be for me to watch you manipulate circuits in lab. The assignments are meant to focus your learning on specific important subjects but just because I haven't assigned a subject explictly doesn't mean that you shouldn't know it. If it is in the reading assignment or lectures, it is important.

The Exams will sample the depth of your understanding in representative areas. But don't forget that much of what we work on this quarter will soon be obsolete so the most important thing for you to do will be to learn how to learn.

Worst Case Grading criteria

Two exams 300
About six formal assignments 300
Total 600
Exams - ~80% for 4.0 50% for 0.0

Back


Back to the Table of Modules

 




 






 






Lab Assignment 12. -------Final Project Note: This assignment may change

You will design and build aprogrammable, resetable combination lock
Inputs:   BCD value from a keyboard -- four bit bus
              Unlock     -- one bit input, true to unlock if the combination is correct
               Program   ---  One bit input -- true to ibegin reprogramming the combination -- Only operable when lock is open

Outputs:  Unlocked   =-- True when the lock is unlocked

Operrateon:   User enters three numbers;  If the numbers are correct, in the right sequence, the lock opens when the opne input is activated. Otherwise, the lock is locked.
                     While open, any number input from the keyboard relocks the lock.                     

To change the combination
            First unlock the lock. While unlocked (open), set program to one. The program function will latch, so the program key can be released.
             Enter the new combination and press open, the open signal will go true
             Re-enter the new combination. If they are the same, the combination has been  changed. If they don't compare, the lock reverts to its previous combination.

Return to the schedule

Return to top



Lecture Assignment 1. ---Combinatorial Logic -

Lecture assignment 1, due at the beginning of week 3

From the textbook pages 47-51:

Problems 2.3,  2.4,   2.8,   2.13,   2.18
 

From textbook pages 74-76

Problems 3.10,  3.11,  3.15,  3.17,  3.22
 

Write a brief justification for using only NAND gates in switching logic circuits.  How does it work?  Why does it work?  

 

 






Lecture Assignment 2. ---

Lecture assignment:

Chapter 4  --  4.1, 4.8   

 A      Explain  the operation of a 4 bit 2ís complement adder/ subractor.  Illustrate with truth tables and figures if appropriate.  What are the consequences of the four permutations of the overflow bit?

 B.     A box has two data inputs, A and B and two outputs A and B.
Design a circuit that will reliably allow the user to select channel A or B and move it from input to output.

Chapter 5   --- 5.8, 5.19,   5.24

 

 

Latches, flip-flops, counters ----

Latches:  Discuss the operation of latches thoroughly.  How may they be used in real world situations?

Flip-Flops: Discuss and document the operation of the standard D- Flip-Flop (7474)

Ripple Counters:
  • Show how D flip-flops may be used to construct a four bit register
  • Ripple counters
  • Show how you would design a four bit counter that counts 01230123...
  • Show how you would design a four bit counter that counts  32103210...
  • Show how you would design a four bit counter that counts 01234567890123456789...
  •     How can you make a counter that does not have the problem with rippling zeros?

Return to the schedule

Return to top



Lecture Assignment 3. --Dish Washer Controller-----

In this discussion we will design a complete controller for a simulated dishwasher with 9 controllable cycles and two wash settings.  We will first define the timing then design a circuit which will execute all appropriate functions.

Timing:
Cycle 0:    Everything is off
Cycle 1:    Preparation, empty the dishwasher

Cycle
Number
Name of cycle Actuator Time for this cycle
0 Washer is off.  No controls are running   None
1 Preparation A -  Reset everything. Reset  
2 Preparation B - drain water with low speed pump Low speed pump
Exhaust valve
 
3 Fill cycle.  Fill with fill valve Fill Valve  
4 Wash cycle - Recycle with high speed pump High speed pump
Recycle valve
 
5 Drain cycle - drain water Low speed pump
Exhaust valve
 
6 Fill cycle.  Fill with fill valve Fill Valve  
7 Rinse cycle High speed pump
Recycle valve
 
8      
9      

Return to the schedule

Return to top



Lecture Assignment 4. ---Finite State Automata----

FSAs are very useful when the circuit is inherently sequential.  One feature is that they are readily implemented in a PLA or Programmable Logic array.  Read the first part of chapter 8 and practice doing the bubble charts and state tables.  In class we will develop a system which will count 1 6 4 (975)*3 2 0... 

Return to the schedule

Return to top



Lecture Assignment 1. -------

Return to the schedule

Return to top



Lecture Assignment 1. -------

Return to the schedule

Return to top



Useful computer tools


Two, Three and Four variable truth tables

kARNAUGH MAPS


Here is a gate template you might want to use

PAL example:

PALs190logic_files/pal.htm

Back

To Op Amp Exercise

 


Back to the Table of Modules